Industry-leading Course for UG Students

Graduation Program in VLSI

Delve into the intricate world of Very Large Scale Integration (VLSI) with our comprehensive course, offering hands-on expertise in ASIC design flow and cutting-edge tools to master the art of designing complex integrated circuits.

2 year course
Hybrid Course
For UG Students
Industry Tools
Project based learning
Industry Internship
Apply now Download brochure
500+
Students Trained
Multiple
Industry Partners
Design Verification Course

Kickstart your Career in VLSI

This comprehensive program, designed for engineering students, covers the entire ASIC design flow. Master both physical design and SystemVerilog verification over two years, and apply your skills in a final capstone project to prepare for a successful career.

Industry Tools

Hands-on experience with industry-standard tools and methodologies

Expert Mentorship

Learn from industry experts with years of practical experience

Industry-level Project

Apply your skills to a real-world challenge by undertaking an industry-level final year project with Vivartan.

Why Choose Our Course?

  • Skill Up with Academics Master industry skills alongside your regular college academics.
  • Hands-On Projects Real-world projects to build your portfolio
  • Industry Tools Hands-on experience with industry-standard tools and methodologies
  • Industry Internships Coveted internship opportunities
  • Individual Attention In-person training for personalized mentorship from industry experts with years of practical experience.
  • Industry‑level Final Year Project with Vivartan Complete a capstone final‑year project mentored and evaluated by Vivartan — an industry‑grade experience that readies you for real‑world VLSI roles.
24
Month program
9+
Core Modules

Your Learning Journey

Follow a structured path from VLSI fundamentals to industry-ready expertise, with guaranteed job placement at the end.

Milestone 1: VLSI Industry & Physical Design Foundations

Modules Covered:

  • Module 0 – VLSI Industry Orientation
  • Module 2 – Foundations for Physical Design

Outcome:
Gain a strong foundation in VLSI industry workflows, ASIC design flow, device physics, CMOS logic, and semiconductor fabrication basics.

Milestone 2: Standard Cell Design & Layout Mastery

Modules Covered:

  • Module 1 – Standard Cell Design & Layout
  • Module 3 – Standard Cell (Hands-On)

Outcome:
Acquire expertise in standard cell design, layout techniques, verification, and characterization with practical implementation of 500+ cells.

Milestone 3: RTL to GDSII – Physical Design Flow

Modules Covered:

  • Module 4 – Synthesis (Hands-On)
  • Module 5 – Place & Route (Hands-On)
  • Module 6 – STA & PV (Hands-On)

Outcome:
Master the complete physical design flow from RTL to GDSII, including synthesis, floorplanning, placement, routing, STA, and sign-off verification.

Milestone 4: Capstone Project

Modules Covered:

  • Module 7 – Project (Hands-On)

Outcome:
Work on a full industry-grade project, applying synthesis, place & route, timing closure, and sign-off methodologies end to end.

Milestone 5: Verification & Testbench Development

Modules Covered:

  • Module 8 – SystemVerilog for Verification
  • Module 9 – Verification Component/Architecture Development

Outcome:
Build SystemVerilog-based verification environments, develop reusable components, and create structured testbenches aligned with UVM-style practices.

Proven Success Outcomes

Our graduates consistently achieve exceptional career outcomes in the VLSI industry

5L+
Average salary
Multiple
Industry Partners
200+
Vivartan trained candidates in core VLSI companies

Comprehensive Curriculum

10 carefully crafted modules covering everything from VLSI fundamentals to advanced SoC verification and real-world projects.

  • Introduction to VLSI Industry and ASIC Design Flow
  • Demo of Digital Design Flow using Cadence Tools
  • Overview of EDA Tools used in Industry
  • Shell Basics for Engineers
  • Domains in the VLSI Design Industry
  • Design & Fabrication Overview
  • Career Opportunities for Fresh Graduates
  • Top Companies in the VLSI Industry

  • Standard Cell Library Design using CMOS Logic
  • Schematics, Simulation, and Verification
  • TCL Scripting for Automation
  • Power Analysis & PDKs
  • Stick Diagrams & Layout Techniques
  • Layout Failure Mechanisms & Area Estimation
  • Floorplanning: 9-Track and 12-Track Cells
  • Drive Strength, Logical Effort, Multi-Drive Strength Cells, Multi-Vt Cells
  • Physical-Only Cells (Fillers, Taps, Antennas, Decaps, End Caps, Tie Cells)
  • Physical Verification (DRC, LVS, Post-Layout Simulations)
  • Characterization: LEF, LIB
  • Tape-out Collaterals: GDS, Spice Netlist, Model File

Scope: Apply all above techniques to a library of 500+ cells (logic & sequential)

Tools Used: Virtuoso Schematic/Layout, Abstract, Liberty, Genus, Innovus, Tempus, Assura/PVS

  • Device Physics: PN Junction, MOSFETs, I-V Characteristics
  • DC Transfer Characteristics
  • Semiconductor Manufacturing Flow
    • Silicon Manufacturing, Photolithography, Oxide Growth/Removal, Diffusion, Silicon Deposition, Assembly
  • CMOS Logic Fundamentals
    • Logic Gates, Compound Gates, Pass Transistors, Transmission Gates, Tristates, Multiplexers, Sequential Circuits

  • Design of CMOS Logic Gates
  • Schematics & Testbench Generation
  • Transient & DC Analysis
  • Power Analysis & Drive Strength Testing
  • Logical Effort & Optimization
  • Layout Design & Verification (DRC, LVS)
  • Post-Layout Simulations
  • Standard Cell Characterization (LEF, LIB)

Scope: Implementation for 500+ standard cells (logic & sequential)

  • Basics of Synthesis & High-Level Synthesis Flow
  • Reading Verilog RTL Files
  • Target & Link Libraries, Resolving References
  • Reading Hierarchical Designs
  • Applying Constraints (SDC)
  • Analyze & Elaborate Commands
  • Constraining & Compiling RTL
  • Generating Post-Synthesis Reports & Outputs

  • Floorplanning
    • Core Die Sizing, Macro Placement, Blockages
  • Placement Strategies & In-Place Optimization
  • Congestion Analysis
  • Power Planning
  • Scan Chain Insertion & Reordering
  • Global Routing & Detailed Routing
  • Clock Tree Synthesis (CTS)
  • Post-PnR Power Analysis

  • Introduction to STA
  • Delay Models & Library Analysis
  • SDC Constraints for STA
  • Path-Based Timing Analysis & Reports
  • Timing Exceptions & MMMC Analysis
  • Post-Layout STA
  • Crosstalk (SI) Analysis
  • Sign-off STA & ECO Flow
  • Practical STA Debug & Fixes
  • Physical Verification (DRC, LVS, ERC, IR Drop, EM Analysis)

Tools Used: Virtuoso, Liberty, Genus, Innovus, Tempus, Assura/PVS

  • Industry-Standard Project
  • Application of Complete ASIC Design Flow
  • Timing Closure & Sign-off Implementation
  • End-to-End Flow Demonstration

  • Modules, Ports & Blocks (always/initial)
  • Blocking vs Non-Blocking Assignments
  • Data Types: Bit-vectors, Integers, Reals, Enums, Arrays, Structures, Classes
  • Verification-Oriented Coding Practices
  • Interfaces: Ports, Modports, Clocking, Procedural Blocks
  • Connecting DUT & Testbench via Interfaces
  • Interprocess Communication: Fork-Join, Semaphores, Mailboxes

  • Sequencers: Transaction Generation
  • Drivers: Stimulus to DUT
  • Monitors: Capturing DUT Activity
  • Scoreboards: Checking Expected vs Observed Results
  • Agents: Bundling Verification Components
  • Building Reusable Verification Environments

Meet the course instructor

Firstname Lastname
Position
Amet, aliquam id diam maecenas ultricies mi eget mauris pharetra et ultrices neque ornare aenean euismod elementum nisi, quis eleifend quam adipiscing vitae proin sagittis?

Ready to Start Your Journey?

Get in touch with our admissions team to learn more about the course, scholarships, and how we can help launch your VLSI career.

Connect with us directly

Our admission counselors are available to answer your questions.

Chat on WhatsApp Call Us: +91 86180 18435 Email: info@vivartan.com