Physcial Design Course
Elevate your skills in VLSI with our postgraduate program in Physical Design, delving into the art of optimizing chip layouts and mastering tools such as Virtuoso, Genus, and Innovus for efficient and high-performance integrated circuits.
1 year course for college graduates Hybrid - Online/Offline Job Guaranteed Industrial Tool Project based learning

Dive into a transformative one-year journey designed exclusively for recent graduates, focusing on domains across VLSI. Our intensive program is laser-focused on catapulting you into the workforce with a guaranteed job placement. Immerse yourself in hands-on learning with industry-standard tools, mastering Digital Design, Design Verification, Physical Design, AMS Design and Layouts. Our commitment extends beyond training, guiding you through dynamic projects and providing coveted internships, all culminating in a guaranteed job placement. Elevate your career with us, where every aspect of the program is meticulously crafted to ensure your success in the industry.


Optimization Techniques: Immerse yourself in advanced optimization techniques for chip layouts using tools like Virtuoso, Genus, and Innovus. Explore floorplanning, placement, and routing strategies to achieve optimal power, performance, and area (PPA) trade-offs.

Timing Closure Strategies: Navigate the complexities of timing closure in VLSI designs, covering clock tree synthesis, static timing analysis, and signal integrity. Develop skills to meet stringent timing requirements and enhance the overall performance of integrated circuits.

Manufacturability and Yield: Understand the crucial aspects of manufacturability and yield in physical design. Explore techniques to minimize manufacturing variations, enhance yield, and ensure the robustness of VLSI designs.


Module 0

Physical design is a critical phase in the field of integrated circuit (IC) design, where the logical design of a semiconductor chip is transformed into a physical representation suitable for manufacturing. This phase is a crucial step in the development of electronic devices, such as microprocessors, memory chips, and application-specific integrated circuits (ASICs).

MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design online course flow.

Module 1 - Synthesis
  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining Design for timing, area & power
  • Understanding Timing Library (.lib) format.
  • Synthesize Design
  • Timing Checks
  • The report, Analyze and debug results
  • Optimization Techniques
  • Saving the results
Module 2 - Floorplan & Power Routing

Floorplanning involves allocating space for different functional blocks on the chip and arranging them in a way that optimizes the overall chip layout. This step considers factors like power distribution, signal routing, and minimizing the physical distance between critical components to improve performance.

Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines. Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.

Module 3 - Placement

Once the floorplan is established, the placement phase determines the precise locations of individual components, such as transistors, gates, and memory cells. The goal is to minimize wire lengths, reduce power consumption, and enhance signal propagation speed.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.

Module 4 - Timing Analysis & Optimization

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.

Module 5 - Clock Tree Synthesis (CTS)

The clock distribution network is a vital part of chip design, and CTS ensures that clock signals are delivered uniformly to all parts of the chip, minimizing clock skew and improving synchronization.

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.

Module 6 - Routing

After CTS, the routing phase involves establishing the physical paths for signal interconnections. This involves the creation of metal layers and vias that connect various components, ensuring that signals can traverse the chip efficiently.

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.

Module 7 - ECO & Sign-off Checks

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.

Timing closure involves ensuring that the chip meets its performance specifications, like clock frequency and setup/hold time requirements. Designers need to optimize the design to meet these criteria while considering the impact on power consumption and area.

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

Module 8 - Projects
Industry standard projects based on the concepts learnt in the previous modules.

Meet the course instructor

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