Embark on a transformative journey at our institution, where we seamlessly bridge the realms of industry and academia in our cutting-edge undergraduate programs in VLSI and Embedded Systems. Immerse yourself in a curriculum meticulously designed to equip you with hands-on experience using industry-standard tools, delving into the intricacies of ASIC design flow, FPGA technologies, and Microcontrollers. Our commitment extends beyond the classroom, guiding you through placements, fostering dynamic student projects, and providing coveted internship opportunities. Elevate your training with us, where theory meets practice for a comprehensive and industry-aligned learning experience. Experience a course that is uniquely project/task-based, ensuring you not only grasp the concepts but also apply them in real-world scenarios.
Starting with an in-depth introduction to the VLSI industry and ASIC design flow, the course progresses into the intricacies of Standard Cell Design and Layout, covering everything from CMOS Logic to Layout matching techniques. Delve into hands-on experiences with industry-leading tools like Virtuoso, Genus, Innovus, and more, as you master the essentials of Physical Design, Synthesis, and Place & Route. Navigate through Static Timing Analysis (STA), Power Planning, and delve into a real-world project, culminating in a solid foundation in SystemVerilog for Verification and UVM, including advanced topics such as bus protocols AHB, AXI4 Lite, and AXI4 Full. Gain a profound understanding of VLSI, from fundamentals to cutting-edge applications, in this dynamic and practical course.
Design of standard cell library using CMOS Logic, schematics, Simulation and Verification, TCL Scripting, Power Analysis, PDKs, Stick diagrams and layout techniques, Layout failure mechanism, Area estimation and floorplan, 9-Track and 12-Track cells Layout matching techniques, Drive Strength, Logical Effort, Multi Drive strength cells, Multi Vt cells, Physical Only cells, Physical Verification : DRC & LVS, Post Layout simulations, LEF , LIB characterization, GDS, Spice Netlist, Model file, Follow all the above things for set of 500+ cells (Logical Gates, Sequential Gates, Fillers, Taps, Antennas, DeCaps, End Caps, Tie cells)
Tools Used:
Virtuoso Schematic, Virtuoso Layout, Abstract, Liberty, Genus, Innovus, Tempus, Assura/PVS
Device Physics, PN Junction, MOSFETS, I-V Characteristics, DC Transfer Characteristics, Semiconductor Manufacturing, Silicon Manufacturing, Photolithography, Oxide Growth & Removal, Diffusion, Silicon Deposition, Assembly CSMO Logic: Logic Gates, Compound Gates, Pass Transistors, Transmission Gates, Tristates, Multiplexer, Dequential Circuits
Basics of Synthesis, High Level Synthesis Flow, Reading of Verilog RTL File, Target and Link Libraries, Resolving References with Link Libraries, Reading hierarchical Designs, Reading sdc design, Analyze & Elaborate Commands, Constraining and Compiling RTL, Post Synthesis Output Data
Floorplanning:Initial Floor Plan setting, core Die sizing, Macros, Placement blockages, Placement: Placement strategies, in place optimization Congestion analysis, Power Planning, Scan Chains, Global Routing, CTS, Detailed Routing, Power Analysis
Introduction to Static Timing Analysis, Understanding Delays & Libraries, Constraining the design with SDC commands, Timing Analysis of Different Paths, Analyzing Timing Reports, Timing Exceptions, Operating Conditions, Check timing by loading different .libs, Post Layout STA, Multi-Mode Multi-Corner Analysis(MMMC), Cross Talk (SI) Analysis, Sign-off STA & ECO Flow, Practical STA Issues and Solutions
Tools Used: Virtuoso Schematic, Virtuoso Layout, Abstract, Liberty, Genus, Innovus, Tempus, Assura/PVS
A project based on the concepts learnt in the previous modules
It involves modules with input and output ports, always and initial blocks for behavior definition, and a choice of blocking and non-blocking assignments. It supports various data types, including bit-vectors, integers, reals, enums, arrays, structures, and classes, making it well-suited for both digital design and verification tasks. Understanding these fundamentals and data types is essential for effectively modeling and verifying digital systems using SystemVerilog.
Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.
Fork-join and its controls, Semaphore, Mailbox.
Key components include sequencers, drivers, monitors, scoreboards, and agents. Sequencers are responsible for generating sequences of transactions that are sent to the DUT (Design Under Test), and drivers execute these transactions by driving signals into the DUT. Monitors capture and check DUT activity, while scoreboards track and verify expected and observed results. Agents act as intermediaries, connecting sequencers, drivers, and monitors.
