• ASIC Design Flow
• Introduction to Verification
• Verification Flow
• Testbench Architecture
• Verification Plan

Verification with Verilog is an essential part of digital design, especially when working with field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). Verilog is a hardware description language used for modeling and simulating digital systems, making it a valuable tool for verifying the functionality of your digital designs.

System Verilog is an extension of the Verilog hardware description language, and it's designed to support both hardware design and verification. It incorporates features for modeling complex digital systems, allowing engineers to describe not only the structure of a design but also its behavior.

It involves modules with input and output ports, always and initial blocks for behavior definition, and a choice of blocking and non-blocking assignments. It supports various data types, including bit-vectors, integers, reals, enums, arrays, structures, and classes, making it well-suited for both digital design and verification tasks. Understanding these fundamentals and data types is essential for effectively modeling and verifying digital systems using System Verilog.

Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.

Fork-join and its controls, Semaphore, Mailbox.

It encompasses OOP features such as classes and objects, enabling efficient and organized modeling of complex digital designs. With SystemVerilog, engineers can create modular, reusable components, use inheritance to extend functionality, and leverage polymorphism to enhance design and verification capabilities. This integration of OOP concepts in SystemVerilog fosters a structured and maintainable approach to developing and verifying digital systems, making it an invaluable tool for the ever-evolving field of hardware design and verification.

Randomization allows you to generate random test stimuli, fostering a more comprehensive testing approach. Constraints, on the other hand, define limitations or conditions on the randomized values, ensuring they adhere to specific requirements. By combining randomization with constraints, you can systematically explore various scenarios and corner cases, improving the effectiveness of your verification efforts. These features are particularly valuable in verifying complex digital designs and helping to uncover hard-to-find bugs by stressing the design with diverse and realistic inputs.

The Universal Verification Methodology (UVM) is a standardized and widely adopted framework in the field of electronic design and verification. UVM provides a robust and systematic approach to creating advanced verification environments for digital designs. It offers a set of libraries, guidelines, and methodologies that help engineers design and implement scalable and reusable testbenches, making the process of verifying complex systems more efficient and effective. UVM promotes best practices, such as constrained-random stimulus generation, coverage-driven testing, and advanced debugging techniques, leading to higher quality and more reliable digital designs.

The Universal Verification Methodology (UVM) testbench architecture is a standardized framework for creating robust and efficient verification environments in SystemVerilog. It's built on an object-oriented paradigm and provides reusable components to simplify testbench development. The architecture consists of key elements like the Test, Sequence, Driver, Monitor, and Scoreboard. Testbenches are created by composing these elements, allowing for easy integration of test scenarios, stimulus generation, response monitoring, and result checking. UVM promotes best practices in verification, ensuring scalability and maintainability in complex digital design projects.

Key components include sequencers, drivers, monitors, scoreboards, and agents. Sequencers are responsible for generating sequences of transactions that are sent to the DUT (Design Under Test), and drivers execute these transactions by driving signals into the DUT. Monitors capture and check DUT activity, while scoreboards track and verify expected and observed results. Agents act as intermediaries, connecting sequencers, drivers, and monitors.

SoC Verification involves validating integrated circuits with multiple IPs on a single chip. Engineers learn to design testbenches for functional and performance verification, ensuring correct operation and meeting speed requirements. Mastery of methodologies like UVM and formal verification is crucial for efficient testing. A deep understanding of SoC architecture, protocols, and communication is essential to detect and resolve issues early in the design cycle.

Industry standard projects based on the concepts learnt in the previous modules.